数字SoC后端工程师
工作职责
- 完成SoC顶层或模块门级网表到GDSOUT的数字电路物理实现工作，包括FloorPlan，APR，CTS，STA，PV，ELE等；
- 协同前端人员完成STA、功耗分析、SI/PI分析，并优化时序、功耗、面积；
- 完成物理验证，包括DRC、LVS、ERC、ANT等；
- 完成功耗压降分析，包括static/dynamic ir-drop、sem等；
- 使用c-shell/perl/tcl/python等语言编写程序辅助自动化流程。
任职要求
- 本科及以上学历，电子工程、微电子、集成电路、通信、电磁场与微波等相关专业，3年以上数字后端设计相关经验；
- 熟悉数字后端布局布线、时钟树综合、寄生参数抽取、时序分析、信号完整性分析、功耗压降分析、物理验证等设计流程；
- 熟练运用Synopsys/Cadence/Calibre等后端相关的EDA工具，熟悉芯片低功耗设计流程；
- 熟悉Linux操作系统、熟悉cshell/tcl/perl/Python等编程语言、并能熟练运用以辅助设计开发；
- 具有16nm以下工艺SoC设计经验优先；
- 具有自我驱动力、团队合作精神、良好的沟通表达能力。
Responsibilities
- Complete the physical implementation of SoC top-level or module gate-level netlist to GDSOUT, including FloorPlan, APR, CTS, STA, PV, ELE, etc.;
- Collaborate with frontend personnel to perform STA, power analysis, SI/PI analysis, and optimize timing, power, and area;
- Conduct physical verification, including DRC, LVS, ERC, ANT, etc.;
- Completion of power analysis, including static/dynamic ir-drop, sem, etc.;
- Write programs to assist in automating processes by c-shell/perl/tcl/python.
Requirements
- Bachelor's degree or above in Electronic Engineering, Microelectronics, Integrated Circuit, Communication, Electromagnetic Fields, and Microwave, or related majors, with more than 3 years of relevant experience in digital backend design;
- Familiar with digital back-end place and route, clock tree synthesis, parasitic parameter extraction, timing analysis, signal integrality analysis, power consumption and voltage drop analysis, physical verification and other design flows;
- Proficient in Synopsys/Cadence/Calibre and other back-end related EDA tools, and familiar with chip low-power design flow;
- Familiar with Linux operating system, cshell/tcl/perl/Python and other programming languages, and be able to use proficiently to assist the design and development;
- Experience in SoC design for processes below 16nm is preferred;
- Self-driven, team player, good communication skills.
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