High-Speed IP/IO Verification Engineer

Responsibilities:

understand the SPEC of high-speed SerDes IP, and be responsible for the verification of high-speed SerDes IP;

build UVM verification platform for high-speed SerDes IP;

develop validation plans, test pattern and fullregressionpattern;

runs RTL-level and Gate-level simulation and regression simulations.

Requirements:

Electronic Engineering or related major or Computer Science;

2 + years of digital verification experience;

familiar with SerDes verification experience is preferred;

familiar with ASIC design and verification process, with deep understanding of UVM verification methodology;

Proficient in system Verilog and C language, strong scripting skills (Perl,TCL,Python)

Self-driven, team spirit, good communication skills.