High-Speed IP/IO Front-End Engineer

Responsibilities:

Responsible for the design and implementation of SerDes IP;

responsible for algorithm design, RTL programming, simulation design modeling, verification, synthesis, timing convergence and chip debugging;

and simulation design team system interface definition;

and validation team cooperation for integration of the top-level test environment;

and product teams work together to bring a product or IP up to production standards.

Requirements:

electronic engineering or related major or computer science;

2 + years of digital design experience;

10Gps or above SerDes direct development experience is preferred;

strong ability of Verilog RTL programming and simulation;

strong scripting skills (C,Perl,TCL,Matlab);

experience in high speed SerDes design such as Ethernet/PCIe/SATA/USB/MIPI/DDR is preferred;

Self-driven, team spirit, good communication skills.