Design for Testability (DFT) Engineer

Responsibilities:

Design and verify the DFT design of the chip;

Generate test vectors, organize test documentation, cooperate with ATE engineers for debugging, and solve problems in the test process;

Improve the test design flow of the chip;

Support the vectors involved in the reliability assessment of the chip;

Support chip failure analysis.

Requirements:

Bachelor’s degree or above, majoring in Computer Science, Electronic Engineering, Microelectronics, Integrated Circuits, Communication, Electromagnetic Fields and Microwave and other related majors, more than 3 years of DFT experience;

Proficient in using EDA tools and mastering DFT principles and methods;

Familiar with Tessent / TetraMax / Synopsys / Mentor and other testing design tools;

Familiar with Linux operating system, programming languages such as cshell/ tcl/ perl/ Python, etc., and be able to use them proficiently to assist in design and development;

Self-driven, team player, good communication skills.