Digital SoC Backend Engineer

Responsibilities:

Complete the physical implementation of SoC top-level or module gate-level netlist to GDSOUT, including FloorPlan, APR, CTS, STA, PV, ELE, etc.

Collaborate with frontend personnel to perform STA, power analysis, SI/PI analysis, and optimize timing, power, and area;

Conduct physical verification, including DRC, LVS, ERC, ANT, etc.;

Completion of power analysis, including static/dynamic ir-drop, sem, etc.;

Write programs to assist in automating processes by c-shell/perl/tcl/python.

Requirements:

Bachelor's degree or above in Electronic Engineering, Microelectronics, Integrated Circuit, Communication, Electromagnetic Fields, and Microwave, or related majors, with more than 3 years of relevant experience in digital backend design;

Familiar with digital back-end place and route, clock tree synthesis, parasitic parameter extraction, timing analysis, signal integrality analysis, power consumption and voltage drop analysis, physical verification and other design flows;

Proficient in Synopsys/Cadence/Calibre and other back-end related EDA tools, and familiar with chip low-power design flow;

Familiar with Linux operating system, cshell/tcl/perl/Python and other programming languages, and be able to use proficiently to assist the design and development;

Experience in SoC design for processes below 16nm is preferred;

Self-driven, team player, good communication skills.